`timescale 1ns/1ns

module tb();

reg clk_50m;
reg clk_20m;
reg rst_n;
wire [15:0] q;

initial	begin
    clk_50m = 0;
    clk_20m = 0;
    rst_n = 0;
    #100 rst_n = 1;
end

always #10 clk_50m = ~clk_50m;
always #25 clk_20m = ~clk_20m;

quartus_fifo_top inst_top(
    .clk_50m                        (clk_50m),
    .clk_20m                        (clk_20m),
    .rst_n                          (rst_n),
    .q                              (q)
);

endmodule 